1. Field of the Invention
The present invention relates to a laminated chip package including a plurality of laminated chips, a semiconductor substrate for manufacturing the laminated chip package and a method of manufacturing the laminated chip package.
2. Related Background Art
In recent years, electronic devices such as cellular phones and notebook personal computers need to be reduced in weight and improved in performance. With such needs, higher integration of electronic components used for the electronic devices has been required. Further, the higher integration of electronic components has been required also for increase in capacity of a semiconductor memory device.
Recently, System in Package (hereinafter referred to as a “SIP”) has attracted attention as a highly integrated electronic component. The SIP is a device created by stacking a plurality of LSIs and mounting them in one package, and a SIP using the three-dimensional mounting technique of laminating a plurality of chips has received attention recently. Known as such a SIP is a package having a plurality of laminated chips, that is, a laminated chip package. The laminated chip package has an advantage that speed up of operation of circuits and reduction in stray capacitance of wiring become possible because the length of the wiring can be reduced as well as an advantage of capability of high integration.
Known as the three-dimensional mounting techniques for manufacturing the laminated chip package include a wire bonding system and a through electrode system. The wire bonding system is a system of laminating a plurality of chips on a substrate and connecting a plurality of electrodes formed on each of the chips and external connecting terminals formed on the substrate by wire bonding. The through electrode system is a system of forming a plurality of through electrodes in each of the laminated chips and realizing wiring between the chips by the through electrodes.
The wire bonding system has a problem of a difficulty in reducing the spaces between the electrodes in a manner that the wires are not in contact with each other, a problem of a difficulty in speeding up the operation of circuits because of a high resistance value of wires, and a problem of a difficulty in reducing the thickness.
Though the above-described problems in the wire bonding system are solved in the through electrode system, the through electrode system has a problem of increased cost of the laminated chip package because many processes are required for forming the through electrodes in each of the chips.
Conventionally known methods of manufacturing the laminated chip package are those disclosed, for example, in U.S. Pat. Nos. 5,953,588 and 7,127,807 B2, for example. In U.S. Pat. No. 5,953,588, the following manufacturing method is described. In this manufacturing method, first, a plurality of chips cut out of a wafer are embedded in an embedding resin. Then, a plurality of leads to be connected to the chips are formed to create a structure called Neo-Wafer. Subsequently, the Neo-Wafer is cut to create a plurality of structures called Neo-chips each including the chip, the resin surrounding the chip, and the plurality of leads. In this event, end faces of the plurality of leads connected to the chips are exposed on side surfaces of the Neo-chips. Then, a plurality of kinds of Neo-chips are laminated to create a laminated body. In this laminated body, the end faces of the plurality of leads connected to the chips at the respective layers are exposed on the same side surface of the laminated body.
Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December, 1999 describes that a laminated body is formed by the same method as the manufacturing method described in U.S. Pat. No. 5,953,588 and wiring is formed on two side surfaces of the laminated body.
On the other hand, U.S. Pat. No. 7,127,807 B2 discloses a multilayer module which is configured by laminating a plurality of active layers made by forming one or more electronic elements and a plurality of conductive traces on a flexible polymer substrate.